Eligibility:B.Tech/M.tech (ECE,EEE)Skills Required: SV, UVM, Protocol knowledge (PCIe, CXL, Ethernet, DisplayPort, etc.) and Interfaces.Responsibilities:Lead verification team on multiple projectsWork closely with clients, sales/marketing, project managers, design teams to plan and successfully deliver on commitmentsImplement and provide technical guidance to team members on various aspects of verificationResponsible for guiding the team members on protocols, planning and execution of error-related test scenarios.Requirements:Experience and ability to lead a verification teamStrong SV, Classes and UVM conceptsBe able to enforce strict code quality through code reviewBe able to guide the team to deliver effective UVM based Verification plans, test plans and testbench architecturesShould have a strong understanding of functional coverageOne or more Protocol knowledge is a must (PCIe, CXL, Ethernet, DisplayPort, etc.)Strong understanding of either of the interfaces (AXI, AHB, APB, etc.)Strong understanding of constrained randomization in SystemVerilogGood interpersonal skillsGood project planning and execution skills