IC Packaging Engineer

Job Overview

We are seeking a highly skilled and motivated IC Packaging Engineer to join our Advanced Packaging and Hardware Development team. In this role, you will be responsible for the design, development, simulation, and qualification of next-generation semiconductor packaging technologies. You will bridge the gap between silicon design and physical manufacturing, ensuring our integrated circuits (ICs) meet rigorous performance, reliability, and cost standards.

Key Responsibilities

1. Package Design & Development

• Lead the conceptualization, architecture, and detailed design of semiconductor packages (e.g., BGA, QFN/QFP, WLCSP, SiP, 2.5D/3D IC, and Chiplets).
  

• Generate package substrate layouts, ball maps,bond diagram and ball assignments while optimizing for signal integrity, power integrity, and thermal performance.
  

• Collaborate with silicon design teams to define bump/pad configurations and co-optimize the Die-Package-Board interface.
  

• Hand on experience in designing high speed signal layout.
  

2. Modeling & Simulation

• Perform thermal, mechanical, and thermo-mechanical stress simulations (using FEA tools like ANSYS, Abaqus, or Icepak) to predict package warpage, reliability risks, and thermal dissipation.
  

• Conduct electrical simulations to assess parasitic resistance, inductance, and capacitance (RLC$) metrics.
  

3. Vendor & OSAT Management

• Partner with Outsource Semiconductor Assembly and Test (OSAT) vendors and substrate suppliers to drive new package prototyping and mass production.
  

• Evaluate vendor capabilities, review technical specifications, and resolve manufacturing yield issues.
  

Requirements

Required Qualifications & Skills

Education & Experience

• Education: Bachelor’s, Master’s, in Materials Science, Mechanical Engineering, Electrical Engineering, Microelectronics, or a related field.
  

• Experience: 2+ years of hands-on experience in semiconductor packaging design or manufacturing
  

Technical Skills

• Design Tools: Proficiency in package layout tools such as Cadence APD/Allegro or Altium.
  

• Simulation Tools: Experience with ANSYS (Mechanical/Icepak/HFSS), Cadence Sigrity, or COMSOL.
  

• Industry Knowledge: Deep understanding of packaging materials (epoxy mold compounds, substrates, thermal interface materials, solder alloys) and assembly processes (wire bonding, flip-chip, wafer bumping, encapsulation).
  

• Advanced Packaging: Familiarity with modern trends such as Fan-Out Wafer-Level Packaging (FOWLP), Heterogeneous Integration, and Silicon Interposers is highly preferred.
  

Soft Skills

• Excellent cross-functional communication skills to work effectively with silicon design, foundry, OSATs, and product engineering teams.
  

• Strong analytical and problem-solving mindset with a data-driven approach (e.g., Six Sigma, DOE, SPC).
  

Benefits

What We Offer

• Competitive salary and performance-based bonuses.
  

• Comprehensive health insurance.
  

• Opportunities for continuous learning and professional development in cutting-edge semiconductor technologies.