Role : * Perform detailed block design from system requirements and evolving specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with Synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power, and area goals_Desired Skills:_ * Creating Design Methodology, Micro-architecture, RTL coding in Verilog * Domain knowledge of high speed IP (USB, PCIe, DDR) or Processors (RISC-V or ARM) * Efficient in Coding in Verilog * Creating testbenches in Verilog or UVM * Running simulations using ncsim, vcs or similar tools * Debugging design issues using waveform viewers * Creating SDC and UPF constraints for synthesis. * Understanding timing reports. * Equivalence checking using formality or conformal.
Deep-tech Work India