What You’ll Need: Hands on experience on IP, Subsystem and SoC Design Verification experience Experience in UVM test benches – Developing UVM components like drivers, scoreboards, sequences, constraints, and functional coverage Experience in Testcase and Sequence development in legacy test env. Strong experience in debugging complex issues Experience working on PCIe, DDR is an added advantage. What you will be doing: Beyond building UVM test benches, you will own the full verification cycle, from creating coverage-driven plans to executing, reviewing, and refining for full coverage. This includes setting up and debugging regressions, plus driving all design and verification bugs to closure, leveraging proven Python, Shell, TCL, or Perl scripting skills.”