Tessolve 14 May 2026
Digital · Noida, Uttar Pradesh, India, Electronic City, Bengaluru, Karnataka, India, Guindy, Chennai, Tamil Nadu, India, Jubilee Hills, Hyderabad, Telangana, India, ORR, Bengaluru, Karnataka, India, Whitefield, Bengaluru, Karnataka, India · Regular Employee - Probation
Backend EngineeringFrontend EngineeringEmbedded Systems PythonSystemVerilogCAN/LIN
Tessolve 13 May 2026
Digital · Noida, Uttar Pradesh, India, Electronic City, Bengaluru, Karnataka, India, Jubilee Hills, Hyderabad, Telangana, India, ORR, Bengaluru, Karnataka, India · Regular Employee - Probation
Backend EngineeringFrontend EngineeringEmbedded Systems PythonSystemVerilogCAN/LIN
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
VLSI PythonVerilogRTL Design
Logic Fruit Technologies Date not provided
Gurugram/Bengaluru
VLSIFPGA VerilogSystemVerilogVHDL
Innosilica Date not provided
Bangalore, Hyderabad, Noida
VLSI ARMRTL DesignSynopsys
Innosilica Date not provided
Bangalore, Hyderabad, Noida
VLSISemiconductor DesignElectrical Engineering VerilogVHDLVerification
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
VLSI VerilogARMRTL Design
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
VLSI VerilogSystemVerilogVHDL