Moschip 24 Jun 2026
ASIC Design · Bangalore, Hyderabad · Full Time
VLSI VerilogRTL DesignVerification
Moschip 18 Jun 2026
ASIC Design · Bangalore, Hyderabad · Full Time
VLSI VerilogRTL DesignVerification
Moschip 18 Jun 2026
ASIC Design · Bangalore, Hyderabad · Full Time
VLSI VerilogRTL DesignVerification
Moschip 16 Jun 2026
ASIC Design · Bangalore, Hyderabad · Full Time
VLSI VerilogRTL DesignVerification
Tessolve 14 May 2026
Digital · Noida, Uttar Pradesh, India, Electronic City, Bengaluru, Karnataka, India, Guindy, Chennai, Tamil Nadu, India, Jubilee Hills, Hyderabad, Telangana, India, ORR, Bengaluru, Karnataka, India, Whitefield, Bengaluru, Karnataka, India · Regular Employee - Probation
Backend EngineeringFrontend EngineeringEmbedded Systems PythonSystemVerilogCAN/LIN
Tessolve 14 May 2026
Digital · Electronic City, Bengaluru, Karnataka, India, Whitefield, Bengaluru, Karnataka, India, Jubilee Hills, Hyderabad, Telangana, India · Regular Employee - Confirmed
Backend EngineeringFrontend EngineeringEmbedded Systems PythonSystemVerilogCAN/LIN
Tessolve 13 May 2026
Digital · Noida, Uttar Pradesh, India, Electronic City, Bengaluru, Karnataka, India, Jubilee Hills, Hyderabad, Telangana, India, ORR, Bengaluru, Karnataka, India · Regular Employee - Probation
Backend EngineeringFrontend EngineeringEmbedded Systems PythonSystemVerilogCAN/LIN
Tessolve 20 Jan 2026
Digital (TSI_VLSI_DIG) · Whitefield, Bengaluru, Karnataka, India, Guindy, Chennai, Tamil Nadu, India, Jubilee Hills, Hyderabad, Telangana, India · Regular Employee - Confirmed
Frontend EngineeringEmbedded SystemsVLSI Embedded CDFTHardware Design
Moschip 13 Jan 2026
SES · Bangalore, Hyderabad · Full Time
VLSI CC++Verilog
Moschip 8 Jan 2026
SES · Bangalore, Hyderabad · Full Time
VLSI CC++Verilog
Moschip 8 Jan 2026
SES · Bangalore, Hyderabad · Full Time
VLSI CC++Verilog
Moschip 29 Aug 2025
ASIC Design · Hyderabad · Full Time
VLSI VerilogRTL DesignVerification
Morphing Machines Date not provided
Product · Hyderabad · Full Time
AI / Machine LearningEmbedded SystemsFirmware Engineering PythonMATLABARM
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
VLSI PythonVerilogRTL Design
Innosilica Date not provided
Bangalore, Hyderabad, Noida
VLSI ARMRTL DesignSynopsys
Constelli Signals Date not provided
Engineering / FPGA · Hyderabad · Permanent full-time
VLSISoftware Engineering CC++MATLAB
Innosilica Date not provided
Bangalore, Hyderabad, Noida
VLSISemiconductor DesignElectrical Engineering VerilogVHDLVerification
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
VLSI VerilogARMRTL Design
Constelli Signals Date not provided
Engineering / DSP · Hyderabad · Permanent full-time
Embedded SystemsVLSIFPGA PythonCC++
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
VLSI VerilogSystemVerilogVHDL