Role : Perform verification using UVM and SVM on IP, Blocks and top._Desired Skills:_ * Ability to understand RTL quickly * familiar with ASIC/FPGA verification methodology * able to create a Verilog/VHDL module test specification from the ASIC/FPGA functional specification * should have the Knowledge of the System Verilog’s Universal Verification Methodology (UVM)
Deep-tech Work India