SystemVerilog
30 indexed roles.
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Agrani Labs 9 Jul 2026
Vicharak Date not provided
Design Verification Engineer
Vicharak Date not provided
FPGA Developer
XDLINX Space Labs Date not provided
DSP Engineer - Satellite Comms
Sanyark Space Date not provided
Senior FPGA Engineer
Edveon Technologies Date not provided
VLSI Learning and Development Specialist
Pixxel Space 20 Aug 2026
Sr. RTL Design Engineer
Edveon Technologies Date not provided
Senior RTL Design Engineer
Tonbo Imaging Date not provided
FPGA Engineer
QNu Labs 27 Jul 2026
FPGA Verification Engineer
QNu Labs 7 Jul 2026
Head of Hardware Engineering
Tessolve 22 Jun 2026
Manager - Design Engineering
Tessolve 14 May 2026
Sr Design Engineer_1422
Tessolve 14 May 2026
Sr. Design Lead
Tessolve 13 May 2026
Sr. Design Engineer 1
Tessolve 11 May 2026
Design Lead
Astrome Technologies 16 Apr 2026
Lead FPGA Design Engineer
Moschip 13 Jan 2026
Lead Engineer - ASIC Verification
Moschip 8 Jan 2026
Engineer - ASIC Verification
Moschip 8 Jan 2026
Senior Engineer - ASIC Verification
UNMANND 30 Aug 2025
Senior RTL Design Engineer (UAVs)
Moschip 12 Nov 2024
Emulation Engineer
LeadIC Design Date not provided
AMS Verification (DV oriented)
LeadIC Design Date not provided
AMS Verification with Memory
KeenSemi Date not provided
Design Engineer - FPGA
Edveon Technologies Date not provided
Senior Chip Design Verification Engineer
Interex Semiconductor Date not provided
Sr Verification Engineer
Interex Semiconductor Date not provided
Sr/Lead Design Engineer
KeenSemi Date not provided
Technical Lead Engineer-RTL
KeenSemi Date not provided