## Role Overview We are looking for an AMS Verification Engineer with a strong Digital Verification background, proficient in SystemVerilog, UVM, and Verilog, to verify Analog/Mixed-Signal designs at system and interface level. This role focuses on functional verification, protocol checking, coverage, and constrained-random testing of mixed-signal blocks using digital-centric verification methodologies. ⚠️ This is not a circuit-level SPICE verification role. This role is DV-heavy, using AMS co-simulation where required. ## Key Responsibilities → Develop and maintain SystemVerilog / UVM-based verification environments → Create constrained-random testbenches, sequences, scoreboards, and monitors → Verify AMS blocks using digital abstraction models → Perform functional, protocol, and corner-case verification → Integrate analog blocks into SoC / subsystem-level DV environments → Drive coverage closure (functional & code coverage) → Debug failures across RTL, testbench, and AMS interfaces → Collaborate with design and architecture teams to clarify specs and close gaps ## Mandatory Skills & Experience → Strong hands-on experience with SystemVerilog & UVM → Solid proficiency in Verilog / RTL design concepts → Experience in Digital Verification methodologies → Understanding of Analog/Mixed-Signal concepts (ADC, DAC, PLL, SerDes, PHYs, etc.) → Experience with AMS co-simulation flows → Familiarity with EDA tools like Xcelium, VCS, Questa, SimVision, Verdi → Strong debugging skills at testbench and RTL level ## Good-to-Have Skills → Experience with SystemVerilog Assertions (SVA) → Scripting skills in Python / Perl / Tcl → Exposure to UPF / low-power verification → Experience verifying interfaces and protocols (AXI, APB, custom interfaces) → Knowledge of real-number modeling (RNM) ## Ideal Candidate Profile → DV engineer who has worked on mixed-signal designs → Comfortable owning verification from spec to sign-off → Strong problem-solving and debugging mindset → Good communication with cross-functional teams
Deep-tech Work India