FPGA RTL Engineer

Gurugram/Bengaluru · 2 – 15+ Years

Posted: Date not provided
Last verified at source: 9 hours ago

We seek a **skilled and delivery-focused FPGA Engineer** to develop RTL code and implement FPGA-based digital designs, working from specification stage through to system integration. Projects will range from mid-scale to multi-million gate designs involving the latest generation of high-speed serial protocols, DSP pipelines, and control logic — delivered on time and to production quality standards.Job Position : FPGA RTL Engineer (FPGA Design, Verification & High-Speed Interface Development)Experience : 2 – 15+ YearsLocation :Gurugram/BengaluruKey Responsibilities1. Requirements Understanding & Architecture DefinitionCustomer Requirements & Product DefinitionEngage with product and systems teams to thoroughly understand design intent before committing to implementation:Study and interpret customer requirements and product definition documents; raise clarifications and track requirement changesTranslate system-level requirements into block-level technical constraints: gate count budget, clock frequencies, interface bandwidths, and latency targetsParticipate in customer-facing or internal technical reviews to align on scope, schedule, and design assumptionsArchitecture & Detailed Design SpecificationDefine architecture and detailed design specifications based on requirements and evaluated trade-offs:Author micro-architecture documents: block diagrams, state machine descriptions, data path sketches, interface signal definitions, and timing budgetsEvaluate architectural trade-offs: soft IP vs. hard IP, VHDL vs. Verilog coding approach, pipeline depth vs. resource utilization, and clock domain strategiesDefine resource estimates (LUT, FF, BRAM, DSP, SERDES) and present architecture proposals at design review gatesDocument all design decisions and rationale in the engineering design record for traceability through to production2. RTL Micro-Architecture & CodingMicro-Architecture & Module CodingImplement synthesizable RTL for assigned modules across a range of design complexity levels:Code production-quality RTL in VHDL and/or Verilog: state machines, data path pipelines, control logic, FIFOs, arbiters, and bus interfacesImplement high-speed serial protocol logic covering PCIe Gen5/Gen6, USB 3.2, Ethernet 10G/25G/100G, Aurora, and AMBA-AXI interconnectsDesign digital signal processing blocks: FIR/IIR filters, FFT/IFFT pipelines, decimation/interpolation chains, and fixed-point arithmetic unitsImplement memory interface controllers: DDRx, SRAM, and cache management logic optimized for FPGA memory architectureCode peripheral and control interfaces: UART, I2C, SPI, USB, and interrupt controllers with software-accessible register mapsCoding Standards & Design QualityMaintain RTL coding quality and consistency across all assigned design blocks:Apply FPGA-appropriate coding styles: synchronous resets, registered outputs, one-hot FSM encoding, and inference of FPGA primitives (BRAM, DSP, SRL)Follow design-for-verification and design-for-implementation guidelines: avoid combinational loops, latches, and uncontrolled clock gatingPerform self-review and participate in peer design reviews before committing RTL to the design baselineMultiple Clock Domain DesignDesign and implement reliable multi-clock domain architectures:Design clock domain crossing (CDC) structures: synchronizers, async FIFOs, handshake protocols, and multi-bit CDC strategiesDefine and document all clock relationships; classify paths as synchronous, asynchronous, or false for constraint authoringUse CDC analysis tools (Mentor CDC, Cadence Conformal CDC) to verify crossing structures before synthesis3. Verification & Functional Sign-OffTestbench DevelopmentWrite testbenches for assigned modules achieving complete scenario and corner-case coverage:Develop self-checking testbenches in VHDL / SystemVerilog: stimulus generators, response monitors, scoreboards, and coverage collectorsWrite directed tests for nominal operation and constrained-random tests targeting corner cases, protocol violations, and error injection scenariosAchieve functional coverage targets: line coverage, branch coverage, FSM state/transition coverage, and toggle coverage prior to sign-offSimulation & RegressionExecute and manage simulation flows using industry-standard tools:Run RTL and gate-level simulations in ModelSim / QuestaSim / Xcelium; analyze waveforms and debug failures to root causeIntegrate module-level testbenches into team regression suites; triage and resolve failing tests within committed timelinesGenerate and review coverage reports; identify un-exercised scenarios and add targeted tests to close coverage gapsProtocol & Interface VerificationVerify protocol-level behavior for high-speed interfaces:Verify PCIe, USB, Ethernet, AXI, and JESD204B/C interface logic for protocol compliance using BFMs (Bus Functional Models) and VIPValidate ADC/DAC interfaces: data capture timing, sample synchronization, and digital front-end alignmentDocument verification results: test coverage matrix, defect log, waiver rationale, and sign-off status per module release4. FPGA Implementation, Timing Closure & DebuggingFPGA Implementation FlowExecute the full FPGA implementation flow from RTL through production bitstream:Run synthesis in Xilinx Vivado / PlanAhead and Altera Quartus Prime; analyze utilization, timing, and power reports after each runApply physical constraints: pin assignments, I/O standards, Pblock floorplan constraints, and LOC/BEL directives for performance-critical pathsExecute place & route iterations targeting timing closure at required frequency and resource utilization within platform budgetGenerate and validate production bitstreams; manage bitstream configuration and partial reconfiguration flows where requiredTiming ClosureOwn timing closure for assigned partitions based on optimization trade-offs:Author SDC/XDC timing constraints: create_clock, set_input_delay, set_output_delay, set_multicycle_path, and set_false_path directivesAnalyze timing reports: identify critical paths, understand slack distribution, and apply RTL or constraint changes to resolve violationsApply implementation optimizations: pipeline register insertion, logic replication, carry chain usage, and DSP/BRAM packing for density and speed trade-offsIterate through synthesis strategy sweeps and P&R seed exploration to achieve consistent timing closure across design variantsFPGA Debugging & HW/SW IntegrationDebug FPGA designs and support hardware and software integration on target platforms:Debug FPGA designs on hardware using Chipscope Pro / Vivado Hardware Manager (Xilinx) and Signal Tap Logic Analyzer (Altera/Intel)Use external debug equipment: oscilloscopes, logic analyzers, protocol analyzers, and BERTs to isolate signal integrity and functional failuresSupport HW/SW integration: validate register map access, interrupt routing, DMA data transfers, and driver handshake sequences with embedded softwareDiagnose and resolve hardware failures: capture and analyze waveforms, trace data paths, and identify root cause with systematic debug methodologyRequired QualificationsEducation & ExperienceEducation:Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related disciplineExperience:Hands-on FPGA engineering experience including successful completion of at least one FPGA-based product or platform projectProject Track Record:Must have contributed to a complete FPGA project lifecycle — from RTL coding through implementation and hardware bring-up. Simulation-only or purely academic experience does not qualify.Technical Expertise — Core RequirementsRTL Design — Must HaveCoding experience in VHDL and/or Verilog is mandatory — ability to write clean, synthesizable RTL for data path, control, and interface blocksThorough understanding of FPGA-appropriate coding styles: synchronous design, FSM encoding, BRAM/DSP/SRL inference, and registered output disciplinesDemonstrated understanding of speed vs. density trade-offs and how RTL coding choices directly affect synthesis and P&R quality of results (QoR)Experience designing with multiple clock domains: CDC structures, async FIFOs, synchronizers, and clock domain classification for constraintsFPGA Devices & Tools — Must HaveExperience targeting Xilinx and/or Altera FPGAs is required — familiarity with UltraScale+, Zynq, Versal (Xilinx/AMD) or Agilex, Stratix 10 (Intel/Altera)Proficiency with EDA tools: Xilinx Vivado / PlanAhead and/or Altera Quartus Prime for synthesis, P&R, timing analysis, and bitstream generationSimulation tool experience: ModelSim, QuestaSim, or equivalent — ability to run regressions, analyze waveforms, and debug simulation failuresHardware debug tool proficiency: Chipscope Pro, Vivado Hardware Manager (Xilinx) and/or Signal Tap Logic Analyzer (Altera); familiarity with logic analyzers, oscilloscopes, and protocol analyzersHigh-Speed Serial Interfaces — CorePractical RTL implementation experience with high-speed serial protocols: PCIe Gen4/5, USB 3.2, Ethernet 10G/25G/100G, or equivalentExperience with AMBA-AXI / AXI4-Stream interconnect fabric for on-chip bus integration and DMA data flowFamiliarity with transceiver / GT architecture: link training, channel bonding, and protocol initialization sequencesMemory & Peripheral Interfaces — CoreExperience with memory interfaces: DDRx controller integration, timing constraints, and burst access optimizationImplementation experience with peripheral interfaces: UART, I2C, SPI, or equivalent register-based control interfacesFamiliarity with ADC/DAC interfaces for data acquisition and signal processing applicationsDSP on FPGA — AppreciatedExperience in RTL implementation of DSP algorithms: FIR/IIR filters, FFT, decimation/interpolation, and fixed-point arithmetic pipelinesUnderstanding of DSP slice usage (DSP48E2 / DSP58) for multiply-accumulate, SIMD, and complex multiply operationsExposure to radar, communications, or signal processing applications on FPGA is a strong advantageAdvanced Interfaces — AppreciatedDevelopment experience with PCIe Gen5/Gen6, CXL, 200G/400G Ethernet, or JESD204B/C for high-bandwidth platform designsExperience with AMBA APB, AHB, or CHI interconnect protocols for SoC-style FPGA platform architecturesFamiliarity with Vitis AI / Versal DPU for AI/ML inference deployment on FPGA platformsEngineering CompetenciesTechnical OwnershipProven ability to own assigned RTL modules from specification through verification sign-off and implementation closure with minimal supervisionSystematic debug mindset: isolates root cause efficiently in both simulation and hardware using structured analysis techniquesMaintains design documentation, adheres to coding guidelines, and meets design review and coverage gate targetsExecution ExcellenceDelivers RTL blocks, testbenches, and implementation results on committed schedule, flags risks early with proposed mitigationsProvides accurate effort estimates for RTL tasks, verification scenarios, and timing closure iterationsExperienced working within structured development milestones: architecture review, RTL freeze, verification sign-off, and implementation releaseCollaboration & CommunicationCommunicates design decisions, trade-offs, and implementation risks clearly in design reviews and team discussionsWrites clear technical documentation: module specifications, timing constraint rationale, testbench coverage reports, and hardware debug notesWorks effectively with hardware, firmware, and software teams during platform integration, bring-up, and validation phasesWhy This RoleReal Design Complexity:Work on multi-million gate FPGA designs with the latest generation protocols — PCIe Gen5/Gen6, 100G+ Ethernet, JESD204B — not reference designs or eval board exercisesProduct Impact:Your RTL ships in defense systems, 5G test platforms, AI accelerators, and robotics platforms used by Tier-1 customers globallyFull Lifecycle Ownership:Own modules end-to-end — specification, RTL coding, verification, timing closure, and hardware debug. Real accountability at every stageInnovation Mandate:Work at the cutting edge of FPGA-AI convergence with Versal AI Core, UltraScale+, and Agilex platforms integrating AI Engines and custom acceleratorsCareer Growth:Clear progression from FPGA Engineer to Senior FPGA Engineer and Principal Engineer with structured mentorship from engineers who have shipped multiple complex productsEquity Upside:Meaningful ESOP allocation in a company transitioning from bootstrapped to VC-backed growthCompensation & BenefitsSalary commensurate with relevant experience, expertise, and skills.Performance Bonus: Annual bonus tied to individual delivery milestones and team OKRsBenefits: Health insurance, flexible work options, and paid leaves.Equity:ESOP allocation commensurate with seniority and contribution