_**Key Responsibilities:**
Develop UVM-based verification environments for FPGA RTL blocks and subsystems.
Write comprehensive test plans, and implement stimulus, checkers, monitors, and scoreboards.
Ensure functional correctness via SystemVerilog assertions, constrained-random testing, and coverage closure.
Analyze simulation failures and debug RTL with tools like QuestaSim/ModelSim/Vivado and waveform viewers.
Collaborate with RTL designers and systems engineers to understand requirements and corner cases.
Participate in code reviews, design documentation, and DO-254 verification artifacts.
Contribute to integration and validation efforts on target hardware platforms (Xilinx/Intel FPGAs)._
_**Required Qualifications:**
B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.
3+ years of experience in FPGA verification.
Hands-on expertise with SystemVerilog, UVM, and functional coverage techniques.
Experience with verification tools like QuestaSim, Vivado Simulator, or VCS.
Familiarity with scripting languages (TCL, Python, Perl) for simulation automation.
Understanding of communication protocols like SPI, UART,I2C standards._ _Understanding of AXI and AVALON protocols.
Strong analytical, problem-solving, and communication skills._
Deep-tech Work India