QNu Labs 27 Jul 2026
Bangalore · Full-time
FPGASemiconductor Design VerilogSystemVerilogVHDL
QNu Labs 7 Jul 2026
Bangalore · Full-time
Embedded SystemsVLSIFPGA SystemVerilogVHDLLinux
Moschip 24 Jun 2026
ASIC Design · Bangalore, Hyderabad · Full Time
VLSI VerilogRTL DesignVerification
Moschip 18 Jun 2026
ASIC Design · Bangalore, Hyderabad · Full Time
VLSI VerilogRTL DesignVerification
Moschip 18 Jun 2026
ASIC Design · Bangalore, Hyderabad · Full Time
VLSI VerilogRTL DesignVerification
Moschip 16 Jun 2026
ASIC Design · Bangalore, Hyderabad · Full Time
VLSI VerilogRTL DesignVerification
Tessolve 14 May 2026
Digital · Noida, Uttar Pradesh, India, Electronic City, Bengaluru, Karnataka, India, Guindy, Chennai, Tamil Nadu, India, Jubilee Hills, Hyderabad, Telangana, India, ORR, Bengaluru, Karnataka, India, Whitefield, Bengaluru, Karnataka, India · Regular Employee - Probation
Backend EngineeringFrontend EngineeringEmbedded Systems PythonSystemVerilogCAN/LIN
Tessolve 14 May 2026
Digital · Electronic City, Bengaluru, Karnataka, India, Whitefield, Bengaluru, Karnataka, India, Jubilee Hills, Hyderabad, Telangana, India · Regular Employee - Confirmed
Backend EngineeringFrontend EngineeringEmbedded Systems PythonSystemVerilogCAN/LIN
Tessolve 13 May 2026
Digital · Noida, Uttar Pradesh, India, Electronic City, Bengaluru, Karnataka, India, Jubilee Hills, Hyderabad, Telangana, India, ORR, Bengaluru, Karnataka, India · Regular Employee - Probation
Backend EngineeringFrontend EngineeringEmbedded Systems PythonSystemVerilogCAN/LIN
Tessolve 11 May 2026
Digital · Electronic City, Bengaluru, Karnataka, India · Regular Employee - Confirmed
Semiconductor DesignElectrical Engineering PythonSystemVerilogVerification
Moschip 13 Jan 2026
SES · Bangalore, Hyderabad · Full Time
VLSI CC++Verilog
Moschip 8 Jan 2026
SES · Bangalore, Hyderabad · Full Time
VLSI CC++Verilog
Moschip 8 Jan 2026
SES · Bangalore, Hyderabad · Full Time
VLSI CC++Verilog
UNMANND 30 Aug 2025
Bengaluru, Karnataka · Full time
VLSI CC++Verilog
LeadIC Design Date not provided
Engineering · Hyderabad / Bengaluru · Full Time
Semiconductor Design PythonVerilogSystemVerilog
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
FPGA VerilogSystemVerilogVHDL
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
VLSI PythonVerilogRTL Design
Krisemi Design Date not provided
Hyderabad/Bangalore
Semiconductor Design Verification
Innosilica Date not provided
Bangalore, Hyderabad, Noida
Semiconductor Design CC++ARM
Logic Fruit Technologies Date not provided
Gurugram/Bengaluru
FPGA SystemVerilogEmbedded CRTL Design
Suind Date not provided
Production · Bengaluru, Karnataka · Full Time
Aerospace Engineering LinuxVerificationPropulsion
Krisemi Design Date not provided
Bangalore
Semiconductor Design Verification
Logic Fruit Technologies Date not provided
Gurugram/Bengaluru
VLSIFPGA VerilogSystemVerilogVHDL
Innosilica Date not provided
Bangalore, Hyderabad, Noida
VLSISemiconductor DesignElectrical Engineering VerilogVHDLVerification
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
VLSI VerilogARMRTL Design
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
Semiconductor Design PythonVerificationSoC Design
Innosilica Date not provided
Bangalore, Hyderabad, Noida
Semiconductor Design VerilogVerificationPhysical Design
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
Semiconductor Design VerificationSoC Design
KeenSemi Date not provided
Noida, Bangalore and Hyderabad
Semiconductor Design VerilogSystemVerilogVHDL
